The present invention relates to the communication of signals, in particular, to the transmission and reception of digital signals. More specifically, the present invention relates to encoding and decoding the data being sent to guarantee the minimum and maximum pulse width of the signal taking 12 bits per signal when the data payload rate is above the bandwidth of the channel.
The present invention is particularly applicable to interfaces between integrated circuits and for high speed communications, such as currently addressed by Asynchronous Transfer Mode (ATM), 10 Gigabit Ethernet, PCI Express, RapidIO, Hyperchannel and Fibre Channels, and makes possible yet higher data rates for a particular bandwidth of the transmission medium or to increase the maximum channel length or reduce the bit error rate.
As the operating frequency of complex digital communication and data transfer systems increases, one of major technical challenge has been to improve the data transmission when the data rate is about or exceeds the bandwidth of a communication channel. A conventional communication channel comprising a differential driver, such as an LVDS (Low Voltage Differential Signaling) driver, a production package for the integrated circuit such as a BGA (Ball Grid Array), a printed circuit board, a receiver packaged similarly with its ESD (Electronic Static Discharge) structure, acts together as a filter.
The use of transmission codes to improve the received characteristics of the information is well known in the prior art.
For example, 8 b/10 b encoding is commonly used to ensure there are sufficient transitions present in the bit stream, i.e. having maximum pulse limited by 5 bit intervals, to make clock recovery possible, as in U.S. Pat. Nos. 4,420,234 and 4,486,739. The 8 bits are transmitted during 10 bit intervals, that is not efficient when the data rate is limited by the maximum frequency of the signal spectrum. Still, it is commonly used nowadays. One of the most advanced known for today coding scheme to achieve the higher data rate through the bandwidth limited channel is the one that converts 8-bit digital data into 14-bit digital modulation codes (the so-called EFMxe2x80x94eight-to-fourteen modulation), see, for example U.S. Pat. No. 4,988,999. The advantage is due to doubled pulse width which allows for the packing of 8 bits into 7 bit intervals having the same maximum frequency.
In our earlier U.S. application Ser. No. 10/079,260, filed 21, Feb. 2003, another approach is disclosed providing 8 to 13 coding scheme. According to this invention, one byte is coded by 13 bits so that in a serialised stream of data there are no single bit width pulses, such as . . . 0-1-0- . . . Typically, having 13 bits is sufficient to have more than 256 symbols to code one byte (8 bits) and extra command symbols. This is due to doubled pulse width which allows for the transmitting of 8 bits using 6,5 bit intervals having the same maximum frequency of the signal spectrum.
However, in this case, it would be evident that 12 bits would be insufficient because it gives only 233 symbols. Thus, there is a demand for further increasing the data rate, especially, in cases when a DC balance is not necessary, e.g. in chip-to-chip communications, to achieve transmitting of 8 bits using 6 bit intervals having the same maximum frequency of the signal spectrum.
It is an object of the present invention to increase the maximum amount of data that can be communicated across a channel, in the case where the transmitter and receiver can operate at a frequency well above the bandwidth of the transmission medium but the transform or filter function imposed by the transmission medium distorts the signal such that it cannot be sampled reliably.
It is still another object of the invention to reduce the offset of the data from the sampling threshold that occurs as a function of the data pattern when the data rate exceeds the bandwidth of the channel.
In accordance with these and other objects, the present invention is a coding apparatus for coding data represented by input symbols into codes for transmitting the codes by a transmitter along a communication channel serially, the codes being represented in the channel by signals having a limited minimum and maximum pulse width, wherein the input symbols are encoded to have the minimum signal pulse width longer than one period of the receiver""s sampling clock; the apparatus comprising:
a means for generating a coding table wherein two symbols are coded in conjunction with one another; the table comprising 466 symbols grouped into 233 pairs so that, within each pair, one symbol is complementary to another one, to obtain the coding table comprising only 233 symbols such that no one symbol is complementary to another symbol;
a means for partitioning the obtained coding table comprising 233 symbols into three groups of symbols, including:
a first group comprising one symbol only, wherein all bits are the same;
a second group comprising symbols in which two least bits are the same; and
a third group comprising symbols in which the two least bits are opposite.
The code table may be reordered to provide the optimal coder implementation such as having minimal logical terms. For example, a modification of the table of the first embodiment gives a fast and elegant means to enable 8 bit input symbols encoding into 12 bit output codes. In this case, the constraints include: minimal pulse width is 2, maximal pulse width is 22, code word width is 12. An implementation of the coder/decoder means for a table corresponding to these requirements can be implemented as presented in Appendix A.
The example implementations of a coder and decoder are presented in appendices A and B in RTL (register transfer level) Verilog.
Using a similar technique, the number of coding combinations for 13 bit symbols with minimum pulse width 2 can be increased to the amount sufficient to code two 8 bit symbols with DC balance enhancement. A typical procedure including DC balance is described in detail in U.S. application Ser. No. 10/079,260 filed 21, Feb. 2002 by the same inventors, the specification of which application being incorporated herein by reference.
In still one more aspect of the invention, a communication apparatus is provided comprising a coding apparatus according to the first aspect of the invention, a serialiser, a communication channel, a deserialiser and a decoder.
A coding apparatus, or, coder as well as the decoding apparatus, or coder, can be implemented in hardware, such as a hub, switch, router, modem or processor, or in a CD, or disc driver, as well as in a logic element synthesised or created based on a table listing of the code alphabet. Alternatively, the coder or decoder may be implemented in a lookup table.
The code table may be splitted into subtables and an intermediate code may be computed from which the final code is determined.
In another aspect of the invention, a method of coding data represented by input symbols into codes for transmitting along a communication channel is provided using the coder of the first aspect of the invention.
In still another aspect of the invention, a communication system and a method of communication is provided including coding data represented by input symbols into codes, transmitting the codes along a communication channel, and receiving data, wherein the data are coded using a method of coding of the present invention.
Further, a method of decoding codes into respective output symbols is provided.